`include "BUS.v"
`include "Y86.v"
`include "sram.v"
module TB_Y86(
////////////////////	Clock Input	 	////////////////////	 
/*CLOCK_27,						//	27 MHz
CLOCK_50,						//	50 MHz
EXT_CLOCK,						//	External Clock
////////////////////	SRAM Interface		////////////////
SRAM_DQ,						//	SRAM Data bus 16 Bits
SRAM_ADDR,						//	SRAM Address bus 18 Bits
SRAM_UB_N,						//	SRAM High-byte Data Mask 
SRAM_LB_N,						//	SRAM Low-byte Data Mask 
SRAM_WE_N,						//	SRAM Write Enable
SRAM_CE_N,						//	SRAM Chip Enable
SRAM_OE_N*/						//	SRAM Output Enable
);

wire CLOCK_50;
wire CLOCK_27;
wire EXT_CLOCK;

////////////////////////	SRAM Interface	////////////////////////
wire	[15:0]	SRAM_DQ;				//	SRAM Data bus 16 Bits
wire	[17:0]	SRAM_ADDR;				//	SRAM Address bus 18 Bits
wire			SRAM_UB_N;				//	SRAM High-byte Data Mask
wire			SRAM_LB_N;				//	SRAM Low-byte Data Mask 
wire			SRAM_WE_N;				//	SRAM Write Enable
wire			SRAM_CE_N;				//	SRAM Chip Enable
wire			SRAM_OE_N;				//	SRAM Output Enable


reg clk = 0;

reg [31:0] addr;

wire [31:0] tmp_addr;

reg [15:0] data_i;

wire [15:0] tmp_data_i;

reg write = 0;

wire tmp_write;


wire [15:0] data_o;

wire [31:0] chip_addr;

wire [15:0] chip_data_i;

wire [15:0] chip_data_o;

wire chip_write;

wire init_ub;

wire init_lb;


reg reset = 0;

reg write_data;

//assign data_i = (!write)? addr[15:0]: 16'bz;


always #1 clk = !clk;


reg [31:0] cnt = -1;

assign tmp_addr = ((!reset) ? addr : chip_addr);
assign tmp_data_i = ((!reset) ? data_i : chip_data_o);
assign tmp_write = ((!reset) ? write : chip_write);
assign tmp_ub = ((!reset) ? 1 : init_ub);
assign tmp_lb = ((!reset) ? 1 : init_lb);


always @(posedge clk) begin
      cnt = cnt + 1;
      
      case(cnt)
	    0: begin
		  addr = 0;
		  data_i = 16'h8030;
		  write = 1;
	    end
	    
	    1: begin
		  addr = 1;
		  data_i = 16'h0001;
		  write = 1;
	    end
	    2: begin
		  addr = 2;
		  data_i = 16'h0000;
		  write = 1;
	    end
	    3: begin
		  addr = 3;
		  data_i = 16'h8330;
		  write = 1;
	    end
	    4: begin
		  addr = 4;
		  data_i = 16'h0001;
		  write = 1;
	    end
	    5: begin
		  addr <= 5;
		  data_i <= 16'h0000;
		  write <= 1;
	    end
	    6: begin
		  addr = 6;
		  data_i = 16'h0361;
		  write = 1;
	    end
	    7: begin
		  addr = 7;
		  data_i = 16'h0340;
		  write = 1;
	    end
	    8: begin
		  addr = 8;
		  data_i = 16'h007f;
		  write = 1;
	    end
	    9: begin
		  addr = 9;
		  data_i = 16'h0000;
		  write = 1;
	    end
	    default: begin
	      reset <= 1;
	    end
      
      endcase
end


////////////// SRAM /////////////

SRAM ram(.ADDR(SRAM_ADDR), .DATA(SRAM_DQ), .WE_N(SRAM_WE_N), .OE_N(SRAM_OE_N), .UB_N(SRAM_UB_N), .LB_N(SRAM_LB_N), .CE_N(SRAM_CE_N));


////////////// BUS//////////////

BUS b(.MEM_ADDR(SRAM_ADDR),
      .MEM_DATA(SRAM_DQ),
      .WE_N(SRAM_WE_N),
      .OE_N(SRAM_OE_N),
      .UB_N(SRAM_UB_N),
      .LB_N(SRAM_LB_N),
      .CE_N(SRAM_CE_N),
      .INIT_ADDR(tmp_addr[17:0]),
      .INIT_DATA_IN(tmp_data_i),
      .INIT_DATA_OUT(data_o),
      .INIT_WRITE(tmp_write),
      .INIT_UB(tmp_ub),
      .INIT_LB(tmp_lb));
      
      
////////////////Y86/////////////

Y86 y(.CLOCK(clk), .mem_addr(chip_addr), .mem_data_i(data_o), .mem_write(chip_write), .mem_data_o(chip_data_o), .reset(reset), .mem_ub(init_ub), .mem_lb(init_lb), .PC_TB_o(PC),
		.INST_1_B_o(INST_1_B),
		.INST_2_B_o(INST_2_B),
		.STAGE(STAGE),
		.WAIT_o(WAIT));

initial
 begin
    $dumpfile("test.vcd");
    $dumpvars(0,TB_Y86);
 end

 
 initial #500 $finish;

endmodule